1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the bus architecture of data processing systems.
2. Description of the Prior Art
As is illustrated in FIG. 1 of the accompanying drawings, it is known to provide data processing systems including a plurality of processors 2, 4 connected to a common bus 6. Also connected to this common bus 6 is a shared memory 8 which is to be accessed by either of the processors 2, 4. Interrupt controllers 10, 12 for respective ones of the processors 2, 4 are connected via a bridge 14 to the bus 6. The interrupt controllers 10, 12 are not intended to be shared between the processors 2, 4, but nevertheless share the common bus 6.
The arrangement of FIG. 1 has a number of disadvantages. The processor 2 can access either of the interrupt controllers 10, 12 even though it should only really need and be allowed to access the interrupt controller 10. This can compromise the security and integrity of the system. In order that the processors 2, 4 can correctly address their respective interrupt controllers 10, 12 that share the common bus 6, they must run different binary images of the software concerned and are not able to share common software. Since all of the communications are routed over the bus 6, the bandwidth available on this bus is reduced disadvantageously.